FPGA Design and Verification Using MATLAB and Simulink

Etkinlik Programı ve İçeriği

Raghu Sivakumar is a senior product marketing engineer at MathWorks for FPGA, ASIC and SoC Devices. He has been with MathWorks since 2018 and supports MATLAB and Simulink users across industries in the adoption of HDL Coder and HDL Verifier products. Prior to joining MathWorks he worked in the automotive industry as a vehicle software integration engineer. He has a master’s degree in embedded systems and controls from the University of Leicester.

Jack Erickson is responsible for product marketing and product management for the HDL product family at MathWorks. Prior to joining MathWorks, he spent over 20 years at Cadence Design Systems, Inc., as an applications engineer and in product marketing for simulation, RTL synthesis, and high-level synthesis. He has a BSEE from Tufts University and an MBA from Worcester Polytechnic Institute.

1. Model and simulate a hardware-ready signal processing algorithm
2. Explore options to improve hardware efficiency, such as fixed-point conversion and pipelining
3. Generate HDL code and analyze results
4. Generate SystemVerilog DPI testbench components to speed production verification
5. Cosimulate the Simulink model back-to-back with the HDL while measuring coverage

Etkinlik Bilgileri

08 Eylül 2021
14:00 – 15:30
Raghu Sivakumar, Jack Erickson

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